The present invention relates to semiconductor device structures and processing methods, and more particularly to a field effect transistor structure (“FET”) having a body contact.
Speed is a key aspect of operational performance of integrated circuits. In recent years, enhanced fabrication techniques including silicon-on-insulator (SOI) technology have been introduced. SOI technology is becoming increasingly important since it assists in lowering the capacitance of transistors, enabling greater switching speeds. FETs typically have a voltage-controlled source-drain conduction path extending between a source region, through a channel region and into a drain region of the FET. Another way that a FET can be considered is that each FET has two source/drain regions, one disposed at each end of the channel region, instead of making a distinction between the one source region and one drain region. When FETs are formed in bulk substrates, the junctions between the source/drain regions and the well region surrounding the transistor and between the well region and the body of the transistor (the portion of the transistor immediately below the gate including the transistor channel), result in significant capacitance. In SOI substrates, active devices such as field effect transistors (“FETs”) are formed in a relatively thin single-crystal semiconductor layer overlying a buried layer of insulating material such as a buried oxide (BOX) layer. Most of the capacitance associated with the junctions between the source/drain regions and the surrounding well region is eliminated in a design including an SOI substrate, because the heavily-doped source/drain region is isolated from the substrate by the presence of the buried oxide. Moreover, with the presence of the BOX layer under the transistor body in the SOI design, and the gate dielectric on top, and the source and drain regions on the sides, the body of the SOI FET is, as a result, electrically isolated.
The electrically isolated body of a transistor having a conduction channel formed in an SOI substrate is known as a “floating body” because the body floats at a potential which varies according to various conditions in which the transistor is operated, wherein such potential is usually not known in advance. In consequence, the threshold voltage VT of the transistor is subject to variation, also to an extent that is usually not known in advance. The threshold voltage VT is the voltage at which an FET transitions from an ‘off’ state to an ‘on’ state. FETs are fabricated as either n-channel type FETs (NFETs) or p-channel type FETs (PFETs). Using the NFET as an example of an FET, the threshold voltage VT may be lowered, causing the NFET to turn on at too low a voltage, early within a switching cycle. This may cause an early or false detection signal for rising signal transitions. Conversely, for falling signal transitions, detection comes later than expected. In addition, a lower value of the low voltage is required to keep the subthreshold leakage current tolerably low. Alternatively, the threshold voltage VT may increase as a result of charge accumulation, causing the NFET to turn on late for rising signal transitions and early in the case of falling signal transitions.
While such variations in the threshold voltage are usually tolerable when the FET is used in a digital switching element such as an inverter or logic gate, FETs used for amplifying signals, especially small swing signals, need to have a stable threshold voltage.
One solution is to provide a body contact for the field effect transistor having a conduction channel disposed in an SOI substrate. A body contact is an electrically conductive contact made to the body of the transistor to provide, inter alia, a low-resistance path for the flow of charge carriers to and from the transistor body.
FIG. 1 is a plan view illustrating a prior art FET 100 having a conduction channel (not shown) formed in a SOI region of a substrate, the FET having a body contact. The particular SOI region in which the FET is formed is also referred to herein as an active area 110, as bounded by one or more isolation regions 122. As shown in FIG. 1, the FET 100 includes a conductor pattern 104 having a gate conductor portion 102 which extends in a direction of the length 115 of the active area 110. The gate conductor portion 102 divides the width 120 of the active area 110 into three parts: a source region 113 disposed between a left edge 106 of the active area and the gate conductor portion 102, a channel region (not shown) of the FET underlying the gate conductor portion 102, and a drain region 114 disposed between the gate conductor portion 102 and a right edge 108 of the active area 110.
FIG. 2 is a sectional view of the SOI FET through line 2—2 of FIG. 1. As shown in FIG. 2, the body 160 of the FET 100 is disposed in an active area 110 of a semiconductor-on-insulator (“SOI”) region such as a silicon-on-insulator layer of an SOI substrate 90. The active area 110 is bounded by one or more isolation regions 122 disposed at left and right edges 106, 108 of the active area 110, as well as at the top edge 124 and the bottom edge 126 of the active area (FIG. 1). The SOI region overlies a buried oxide (“BOX”) layer 103, which insulates the SOI region from a bulk region 107 of the substrate 90. The body 160 of the FET is disposed under the gate conductor portion 102. A channel region 120 occupies a portion of the body 160 close to a gate dielectric 115 of the FET. The source region 113 and the drain region occupy portions of the active area 110 adjacent to the body 160. When the FET is properly biased to conduct by a voltage on the gate conductor 102, current flows across the channel region 120 between the source region 113 and the drain region 114 of the FET.
As shown in FIG. 3, a conductive body contact via 170 conductively contacts a portion of the active area 110 of the FET adjacent to the body 160 of the FET. In a particular example, the FET is an NFET in which the body has p-type doping. The NFET is turned on when a sufficient concentration of electrons accumulates to produce an inversion layer in the channel region 120 (FIG. 1) having n-type conductivity. In such NFET, the body contact has p+ doping in order to provide a conductive path to the p-type doped body 160 of the NFET. This differs from the n+ type doping used for the source region 113 and drain region 114 of the NFET 100 (FIGS. 1–2).
The use of body contacts is particularly advantageous in circuitry involving current sources, current mirror circuits or when used in conjunction with sense amplifiers when data signals need to be amplified. In addition, the body contact designs are used in partially depleted SOI FET devices in order to minimize the floating charge body effects.
However, despite the foregoing advantages of providing a field effect transistor with a body contact, transistor designs include body contacts sparingly because a body contact tends to increase the amount of substrate area that the FET occupies, as well as the capacitance between the gate conductor of the FET and the SOI layer under the gate. Each of these also tends to degrade the performance of the FET in a circuit.
The increase in surface area is best viewed in the top down depiction of FIG. 1, where the conductor pattern 104 includes the gate conductor portion 102 and a large body contact conductor portion 170 connected thereto. The large body contact conductor portion 170, being in capacitive contact with the active area, adds large parasitic capacitance. Moreover, since the area underlying of the large conductor portion 170 does not lie in the area between the source region and the drain region of the FET, the area is not used for driving the on current of the FET as it is for the area under the gate conductor portion 102. The increase in capacitance impacts the switching speed of the FET. The increased area of the large body contact conductor portion further impacts the switching speed of the FET by increasing the length of wiring to the FET. To counter the effects of increased capacitance, the drive current would need to be increased to maintain the original switching speed. Besides being difficult to accomplish, such would cause an undesirable increase in power dissipation.
FIG. 4 is a plan view illustrating a different prior art body-contacted FET 200 in which a body contact conductor portion 270 of the gate conductor pattern has reduced area compared to the area of the body contact conductor portion 170 of FET 100 (FIG. 1). This FET 200 has two gate conductor fingers 202 which extend in a direction of the length 215 of an active area 210, and includes two source regions 213 which are separated from a common drain region 214 by the fingers. The two fingers 202 are placed parallel to each other, dividing the width 240 of the active area 210 into three parts, the two source regions 213 provided between the fingers 210 and the outer edges of the active area 210 and the drain 214 provided between the two fingers 202. The two-finger design of FET 200 is advantageous because it provides increased current drive over a one-finger design of FET 100 which occupies an active area having the same width as width 120 of FET 100 (FIG. 1).
In the prior art FET 200, the body contact conductor portion 270 does not separate the source regions 213 of the active area 210 from the body contact 272, as it did in the FET 100 (FIG. 1). As a result, the source regions 213 are not electrically isolated from the body contact 272. This limits the applications to which the FET 200 can be put, since the voltages applied to the source regions and the body contact must be kept the same, e.g., at ground.
FIG. 5 shows another body-contacted FET 300 according to the prior art. In this FET 300, a body-contact portion 372 of the active area is implanted to p+ doping. This FET 300 has a design which has lowered parasitic capacitance in relation to FET 100 shown in FIG. 1, because the amount of the semiconductor area underlying the body-contact portion 370 of the conductor pattern is less than that shown in FIG. 1. However, the design shown in FIG. 5 is rarely used, because it requires a large amount of semiconductor area 380 to provide the body contact relative to the amount of semiconductor area 390 used to provide the active FET 300.
As mentioned above, one difficulty with the use of a body contact, whether the design shown in FIG. 1, FIG. 4 or FIG. 5 is used, is large parasitic capacitance. The large capacitance arises because of the close proximity between the body contact conductor portion 170 (FIG. 1), 270 (FIG. 4) or 370 (FIG. 5) and the single-crystal SOI region of the substrate across a portion of the gate dielectric layer 115 (FIG. 3).
Consequently, it would be desirable to provide an improved structure and fabrication method for providing a body-contacted FET having reduced parasitic capacitance.